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W5100

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W5100 (WIZnet Hardwired TCP/IP Embedded Ethernet Controller)

Performance Benefits	Line Speed Data transmission by hardwired logic Up to 25Mbps throughput at application layer
Implementation Benefits	Easy & Simple control like memory Save developing time and area
Cost Benefits	Easy TCP/IP implementation without OS MAC & PHY embedded

Block Diagram

Feature

- Support Hardwired TCP/IP Protocols TCP, UDP, ICMP, IPv4 ARP, IGMP, PPPoE, Ethernet
- 10BaseT/100BaseTX Ethernet PHY embedded
- Support Auto Negotiation (Full-duplex and half duplex)
- Support Auto MDI/MDIX
- Support ADSL connection (with support PPPoE Protocol with PAP/CHAP Authentication mode)
- Supports 4 independent sockets simultaneously
- Not support IP Fragmentation
- Internal 16Kbytes Memory for Tx/Rx Buffers
- 0.18 μm CMOS technology
- 3.3V operation with 5V I/O signal tolerance
- Small 80 Pin LQFP Package
- Lead-Free Package
- Support Serial Peripheral Interface(SPI MODE 0, 3)Multi-function LED outputs (TX, RX, Full/Half duplex, Collision, Link, Speed)

Ordering Information

Part No.	Description
W5100	WIZnet Chip Fully Hardwired TCP/IP Chip

Total : 17

TITLE

LANGUAGE

FILE

URL COPY

DATE

W5100 Reference Hardware Schematic R2.1

English

2010-05-26

W5100 Datasheet V1.2.4

English

2011-11-08

This is the W5100 datasheet V1.2.4 Document History Information.

Version	Date	Descriptions
Ver. 1.0.0	Dec. 21, 2006	Released with W5100 Launching
Ver. 1.0.1	Jan. 10, 2006	LB bit in Mode register is not used . W5100 is used only in Big-endian ordering.
Ver. 1.1.1	Jun. 19, 2007	Modified the OPMODE2-0 signals descriptions (P. 10) Modified the TEST_MODE3-0 signals description (P.11) Modified the Clock signals description (P.12) Modified the LINKLED signal description (P.12) Modified the explanation of RECV_INT in Sn_IR register (P. 27) Replaced the reset value of Sn_DHAR register (0x00 to 0xFF, P. 30) Modifted the explanation of Sn_DIPR, Sn_DPORT register(P. 31) Replaced the reset value of Sn_MSS register (0xFFFF to 0x0000, P. 31)
Ver. 1.1.2	Sep. 28, 2007	Modified the Operating temperature (P. 63)
Ver. 1.1.3	Oct. 18, 2007	Changed the typing error “MISO signal” (P. 10) Modified the SPI Timing diagram and description (P. 66)
Ver. 1.1.4	Oct. 18, 2007	Modified the diagram (P. 40)
Ver. 1.1.5	Nov. 11, 2007	Modified the Crystal Characteristics value (P. 67)
Ver. 1.1.6	Jan. 30, 2008	Modified the SEN signals description (P.10) Changed the typing error “SCLK” (P. 66)
Ver. 1.1.7	Feb. 12, 2009	Changed the typing error “memory test mode” (P. 19) Changed the description & type of clock signals (P. 12) Modified DC characteristic value(p. 63)
Ver. 1.2	Feb. 11, 2010	Add the power supply signal schematic (P. 12)
Ver. 1.2.1	Jun. 10, 2010	Add Sn_TX_WR value changing condition
Ver. 1.2.2	Jun. 28, 2010	Modify RD/WR timing diagram (P. 65, 66)
Ver. 1.2.3	Feb. 16, 2011	Change the value of SOCK_ARP(0x01) state (P.31)