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W5100E01-AVR

Product Detail
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Feature

- Data Transfer up to 6Mbps with Atmega128 (8MHz)
- By using External 96pin connectors, AVR&rsquos all pins can be used
- Available of testing SPI Interface
- Provides various application source codes Loopback, Webserver, Ping
- Supports ISP & JTAG Interface

Specification

Category		Specification
Base Board	UART	2 x RS232 serial port
	Display	16 x 2 Text LCD
	PAL	Address Decoder
	TCP/IP	W5100 (PHY Embedde)
	MAG JACK	RDA-125BAG1A, Transformer Integrated (11)
PM-A1	MCU	ATMEGA 128 (128K Flash & 4K EEPROM)
	CLOCK	8MHz Crystal
	External Memory	SRAM (32K Bytes)

Development Environment

- Compiler All source codes are developed by GCC Compiler
- Firmware programming ISP Cable

Contents

	- W5100E01-AVR + PM-A1
	- CD (Source Codes, Schematics, Manuals)
	- 5V 2A Power Adapter
	- Serial Cable, UTP cable

Ordering Information

Model	Description
W5100E01-AVR	W5100E01-AVR + PM-A1

Total : 21

TITLE

LANGUAGE

FILE

URL COPY

AVR Tool Guide

English

W5100E01-AVR User's Guide V1.0 English

English

W5100E01-AVR Hardware Schematic

English

The Address Decode Source of W5100E01-AVR

English

The Partlist of W5100E01-AVR

English

Firmware Source Code of W5100E01-AVR

English

W5100 Reference Hardware Schematic R2.1

English

2007 iEthernet Design Contest Special Archive Edition

English

W5100 Datasheet V1.2.4

English

This is the W5100 datasheet V1.2.4 Document History Information.

Version	Date	Descriptions
Ver. 1.0.0	Dec. 21, 2006	Released with W5100 Launching
Ver. 1.0.1	Jan. 10, 2006	LB bit in Mode register is not used . W5100 is used only in Big-endian ordering.
Ver. 1.1.1	Jun. 19, 2007	Modified the OPMODE2-0 signals descriptions (P. 10) Modified the TEST_MODE3-0 signals description (P.11) Modified the Clock signals description (P.12) Modified the LINKLED signal description (P.12) Modified the explanation of RECV_INT in Sn_IR register (P. 27) Replaced the reset value of Sn_DHAR register (0x00 to 0xFF, P. 30) Modifted the explanation of Sn_DIPR, Sn_DPORT register(P. 31) Replaced the reset value of Sn_MSS register (0xFFFF to 0x0000, P. 31)
Ver. 1.1.2	Sep. 28, 2007	Modified the Operating temperature (P. 63)
Ver. 1.1.3	Oct. 18, 2007	Changed the typing error “MISO signal” (P. 10) Modified the SPI Timing diagram and description (P. 66)
Ver. 1.1.4	Oct. 18, 2007	Modified the diagram (P. 40)
Ver. 1.1.5	Nov. 11, 2007	Modified the Crystal Characteristics value (P. 67)
Ver. 1.1.6	Jan. 30, 2008	Modified the SEN signals description (P.10) Changed the typing error “SCLK” (P. 66)
Ver. 1.1.7	Feb. 12, 2009	Changed the typing error “memory test mode” (P. 19) Changed the description & type of clock signals (P. 12) Modified DC characteristic value(p. 63)
Ver. 1.2	Feb. 11, 2010	Add the power supply signal schematic (P. 12)
Ver. 1.2.1	Jun. 10, 2010	Add Sn_TX_WR value changing condition
Ver. 1.2.2	Jun. 28, 2010	Modify RD/WR timing diagram (P. 65, 66)
Ver. 1.2.3	Feb. 16, 2011	Change the value of SOCK_ARP(0x01) state (P.31)